EDA Deep Dive - Part 1: The History
Breakthroughs, Mergers, and so much more
Disclaimer: Opinions shared in this, and all my posts are mine, and mine alone. They do not reflect the views of my employer(s), and are not investment advice.
The role of Electronic Design Automation (EDA) in the evolution of the semiconductor industry is often underplayed. While chip manufacturers and designers get a lot of credit for maintaining the exponential rate of Moore's law, EDA tools have arguably played as important a role. The earliest chips were hand drawn - imagine doing that for today's chips with over a billion transistors. Without the magic of EDA, using the exponentially increasing number of transistors to create better chips every year would be impossible.
Yet, there is a lot of frustration in the semiconductor industry over these tools - especially when it is compared with the vastly superior war-chest that software developers have access too. There have been some studies, like one by CMU's Electrical and Computer Engineering department, that show that more students have started to pursue software engineering over semiconductor. Among many reasons, I believe a big contributing factor is that the tools used in chip design are either too expensive, very complex to use, or both - which takes the joy out of designing circuits. A lot of people with these complaints either stop using the tools (i.e. change their career), or just accept things the way they are. I have always wondered if, or when we are due for a change in the semiconductor tool flow. Maybe now is the time?
Understanding how this industry has evolved gives a good idea about what to expect. In the past decade, the rules of EDA have been written by 2 major players - Cadence, and Synopsys (and a special mention to Mentor Graphics, now part of Siemens). My goal in this post is to walk through the story of this consolidation.
EDA Gen 1 - The 1970s
Till the 1970s, most chip design was being done by hand - the chip "designer" would draw out the layout of transistors. This drawing was used to create a photomask, and the chip was fabricated using the photomask. To improve productivity, some of the big chip design players started to develop in-house versions of EDA tools. The earliest EDA tools were used to create printed circuit boards (PCBs) - instead of manually wiring different components together, the connections were marked using software. Slowly, similar techniques were developed to create the transistor layout in software. One of the pioneering companies that started the VLSI EDA revolution was LSI logic, who were not only the first to work with new EDA vendors, but also developed their own tools and made them available to their customers (Bigger organization like Intel, Texas Instruments had in-house solutions already, but were kept as proprietary). Seeing this trend, many startups started to emerge that focused specifically on EDA.
The first major development in EDA was to find a way to share details about the transistor layout to semiconductor manufacturers in a digital format (so far, the physical drawing had to be shared). In 1970s, Calma (remember this company, they make an appearance again) created the GDSII file format to store the layout information (it is now commonly known as GDS). These were the first EDA tools - software to convert digital drawings of layouts into a GDS file. Other companies like Applicon and ComputerVision also started to develop these tools.
EDA Gen 2 - The 1980s
The next generation of EDA was led by the founding of Mentor Graphics in the 1980s. During this time, EDA was not merely software - it included huge workstations to run simulations, graphical interface to draw schematics/layouts, and everything else that was needed to moderately automate chip design. So if you bought an EDA tool, you had to buy the whole package. There were many other startups with a similar approach - notably Valid Logic Systems and Daisy Systems Corporation. The biggest advantage of these companies was that they could optimize their tools to run efficiently on the specific workstations they sold. However, this approach also turned out to be their biggest weakness, as during the late 1980s, general purpose computers started to get powerful. This was also the time when the pure-play foundry model started to come up (TSMC was founded in 1987). Fabless chip design started to emerge, and most chip design teams did not want to spend money on expensive workstations that came with the EDA tools. This was a major blow to the EDA industry - most companies from this era died out as they refused to, or just couldn't get their tools to work on general purpose computers. (Mentor Graphics, to their credit, were quick to unbundle their offering, which is why they are the only company major to survive this era.) This was a pivotal moment for EDA - it gave rise to the software-only EDA vendors that we know today.
EDA Gen 3 - 1990 to present
Remember the company Calma from before? In 1981, they were acquired by General Electric (GE). A few years after this, the first Hardware Description Languages (HDLs) were proposed - VHDL (VHSIC Hardware Description Language) in 1983, and Verilog in 1984. One of the employees at GE, Aart de Geus, built a first-of-its kind RTL synthesis tool called SOCRATES - to convert HDL code (called Register Transfer Level, or RTL) into a netlist that could then be used to create a layout. GE was struggling to keep up with the EDA market in 1985, forcing them to shut the division down. As this was going down, Aart de Geus convinced GE to spin off SOCRATES and its related assets into a new company based on North Carolina called Optimal Solutions. Soon, in 1986, they moved the company to Silicon Valley and changed the company name to Synopsys (short for Synthesis Optimization Systems).
During the same time frame, Systems Engineering Laboratories (SEL, one of the earliest microcomputer companies) were experimenting with a tool that reduced errors made by chip designers to produce a functioning chip each time they manufactured one. Called DRaCula (this tool still exists!), SEL build a tool to compare their final transistor layouts with the initial schematic and find errors, if any (this step is now called Layout Vs Schematic, or LVS). In 1982, SEL was acquired by Gould Inc, a battery manufacturing company, which immediately shut down their EDA efforts. Glen M. Antle, who headed the microelectronics products division at SEL, was able to buy the rights for the CAD technologies, and also got $25000 in funding, in exchange for completing some operating system work for their new owner. In 1983, Antle started ECAD, with DRaCula as their crown jewel.
In the same year, Jim Soloman, the director of IC design at National Semiconductor, created tools to streamline the analog design process, and started a company called Solomon Design Automation, or SDA. Both ECAD and SDA were doing very well in their respective fields - in fact they both filed for IPO in 1987. ECAD successfully went public in June 1987, and a few months later, SDA filed to go public. As it turned out, the day SDA was supposed to go public, October 19 1987, was one of the worst days in the US stock market history - known now as Black Monday. SDA's IPO was cancelled, and the recently public ECAD's shared dropped massively. In 1988, both the struggling companies agreed on a merger, and Joseph Costello became the CEO of the new company - which they called Cadence Design Systems.
After this merger, it become clear that there are two behemoths emerging in EDA - Synopsys, focused on front-end VLSI, and Cadence, dominating in backend chip design. In fact, in 1989, Cadence tried to acquire Synopsys to create that one, all-encompassing EDA giant, but Synopsys turned down the offer (Imagine what would have happened if this acquisition went through!) Over the years, both companies acquired other upstarts to each provide a complete suite of tools and dominate this industry. Mentor Graphics, who stuck around through it all, was acquired by Siemens in 2017, and remain a small player today.
This is the story of how the EDA industry came to be. From the 1990s, Cadence and Synopsys have dominated the industry. These are some learnings from this 50 year story:
1. EDA traditionally has a waterfall structure:
Chip design involves architecture design, writing RTL code, Functional Verification, Physical Design, and finally manufacturing the chip. The goal is to develop tools independently to optimize each of these steps. New tools can emerge for each step, or even sub-steps (major companies were built from tools for single steps in the VLSI design flow like GDS, Synthesis, and LVS). This fact has a major impact on both chip design firms and EDA vendors:
Often, large chip design companies maintain relationships with Synopsys, Cadence, and Mentor Graphics, and use their tools interchangeably based on the needs of each step in their design process.
Knowing this, EDA tools from these companies follow similar standards - like file formats, terms used, output formats, and so on - chip design companies want flexibility, and EDA vendors want to reduce the cost of switching from their competitors.
The EDA industry is a great place for mergers and acquisitions - Cadence/Synopsys acquire startups with better tools, and integrate the new tools with their existing ones - which simultaneously improves their technology, and also eliminates competition.
2. EDA vendors don't get replaced easily:
Unlike in a lot of other industries, I don't see EDA companies dying out because another company has a better product - often, the reason for companies running out of business is a change in the technology landscape (from workstations to general purpose computers), or economic factors (a bad economy). I think there are two main reasons for this.
Firstly, trust is hard-earned in this industry - a minor bug in a synthesis tool could cost a chip design firm millions of dollars.
Secondly, these tools solve insanely hard problems - it not just needs strong understanding of all steps of the chip design process, but it also needs expertise in algorithm design (most steps in chip design are NP Hard problems).
Today, if a new EDA vendor comes up with a better tool, it will still take time for them for them to win the trust of chip design teams. This gives Cadence and Synopsys time to react - they can deploy their own R&D resources to beat the upstart, or acquire them before they cause any real damage.
3. Relationships rule the EDA world:
As I mentioned before, a good relationship with chip design companies can help to build trust, which is key for the EDA vendors. But there is another relationship that is fundamental to how the EDA tools works - with chip manufacturers. As I mentioned earlier, after Calma invented the GDSII file format, layouts could be digitally shared with the foundry. However, every chip manufacturer has their own process - so, in order to generate the GDS, EDA tools use something called a "Process Development Kit (PDK)". This is like a secret recipe used by the foundry to produce chips. Major foundries like Intel and TSMC keep their PDK proprietary, and only share it with the EDA vendors they know and trust (a.k.a Synopsys and Cadence), which creates a bridge for upstarts trying to enter the Physical Design and Layout domain.
This is the end of part 1. Check out the next part here:
EDA Deep Dive - Part 2: Open Source
In EDA Deep Dive - part 1, I covered the rise of commercial EDA - with Cadence and Synopsys emerging as the big winners. While these tools are of the highest quality, there are 2 issues with commercial EDA
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