What does CPU bitness mean?

The number of CPUs that makes them sell

Dec 21, 2024

Disclaimer: Opinions shared in this, and all my posts are mine, and mine alone. They do not reflect the views of my employer(s), and are not investment advice.

When you look at CPU specs, one of the first things you would see is what's called "bitness" - 8 bit, 16 bit, 32 bit or 64 bit CPUs. I thought I knew exactly what this number meant, but some research showed that there is more to this than I initially thought.

In general, the bitness refers to the number of bits on which a CPU operates in each clock cycle. But in a conventional CPU, this could manifest in 4 different attributes of the architecture:

Size of the registers
Size of the memory address
Size of the data bus
Instruction size

Let's explore each of these in detail.

Size of the register:

This is the most commonly used and accepted definition for bitness, especially from a CPU microarchitecture point of view. The registers are general purpose storage elements within a CPU where data is moved before arithmetic operations are performed on them. A crude approximation is that variables used in high-level language programs will each map to a register in the CPU.

The register size usually decides many other aspects of a CPU. For example, the arithmetic operations are typically based on the register size - In a 32 bit CPU, 32 bit adders work on 32 bit registers as inputs to produce 32 bit output stored back in a 32 bit register.

In addition to this, register size also dictates the maximum data width that can be moved within the CPU in one cycle. If register size is 32 bit, and your data width is 64 bit, you can still only write 32 bit data in each cycle to the registers. Register size also impacts address size, since address is usually loaded from the registers.

Although bigger register sizes improve performance, they will result in higher area and power consumption, since all components (ALUs, data buses, memory size, etc) need to get bigger to maximize the benefits of a bigger register.

Size of the memory address:

The number of bits used to address memory from a CPU decides the total number of bits that can be addressed - if memory address is 8 bits, then a total of 2^8 = 256 memory locations can be addressed. The memory that is referred to here is the one that is closest to that CPU - typically a cache memory. Larger address sizes meant that more memory could be addresses, which results in fewer cache misses, and reduced paging.

In early CPUs, the address size did not corelate with CPU bitness - if an 8 bit CPU had address size as 8 bit, only 256 locations could be accessed, which limited the number of applications. There were two approaches adopted to handle this:

Use a bigger address width - by combining data from multiple registers
Translate physical memory addresses into virtual addresses

Both of these methods are still used today. But the change from 32 bit to 64 bit CPUs marked a major shift - 32 bit addresses can access a memory of 4 GB - this is smaller than typical RAMs today. However, 64 bit addresses can access a memory of about 16 billion GB! Hence, addresses beyond the CPU size of 64 bit will not be necessary anytime in the near future.

Size of the data bus:

This was by-far the most misleading attribute. When we talk about data here, the first caveat is that this refers to data within the core of the CPU - i.e. not in the memory subsystem. By that definition, data width usually corresponds to the register size, which also matches with the CPU bitness. But in modern processors, this definition could be confusing - for example, in Single-Instruction-Multiple-Data (SIMD) systems, multiple registers could be read in parallel, which makes the bus size larger. It is also not clear how a bus is defined - since fundamentally, every bit has it's own connection, and a bus is just an abstract collection of these bits.

However, assuming data bus size refers to the size of the data bus connecting to the registers, increasing this size generally means that more bits are processed in a clock cycle, improving the overall performance of the CPU. However, this usually comes with some challenges. Typically, data movement consumes power, and moving more bits means the power consumption is higher. A larger data bus also presents challenges in routing the design which minimizing delays in the chip.

Instruction size:

Instruction size refers to the number of bits used to encode an instruction as per the ISA being used (If you don't know what an ISA is, here's a whole post dedicated to that topic).

Having a bigger instruction is advantageous as more information can be encoded into it. For example, if we have an 8 bit ISA with 8 types of instructions (which need 3 bits to represent), it only leaves 5 bits for other information (like addresses, some constants, etc). This limits performance in some cases. As the number of bits in an instruction increases, it can be packed with more information - which often results in more performant assembly code generated by the compiler.

Using an ISA with bigger instructions is not always better - bigger instructions also need more decoding logic, which impacts pipeline design (more in this post). Changing to an ISA with bigger instructions often needs special handling in the microarchitecture, especially for high frequency designs. Since the instruction is also a form of data moving in the CPU, factors affecting bus width also play a role here.

Among all the attributes mentioned, instruction size is the least likely to match with the CPU's bitness. The main reason for this is that CPUs need to remain backward compatible - i.e. software developed for 32 bit CPUs should continue to work in 64 bit CPUs. Hence, 64 bit CPUs should also be able to run 32 bit instructions. The converse is more tricky - can a 32 bit CPU run 64 bit instructions? There are some designs which do this internally (two 32 bit instructions together represent the 64 bit instruction) - but they are not advertised as 64 bit CPUs as they incur a performance penalty. In addition to all this, CISC ISAs like x86 support variable length instructions, which means a 64b x86 CPU likely supports many different instruction sizes.

In summary, although CPU bitness is widely used to compare CPUs, the exact definition varies. For example, The Motorola 68000 was a 32 bit CPU that had 32-bit registers, 16-bit data bus, 24-bit address bus, and a 16-bit ALU and used a 32 bit ISA. However, changes in bitness have indicated the start of a new generation of CPUs - which played a key role in the evolution of PC and mobile CPU companies. I have highlighted two stories of 64-bit CPUs which brough major changes to the processor industry.

x86-64: How AMD beat Intel to 64 bit CPUs

AMD is well known today as a leader in high performance CPUs. But this was not always the case. AMD was founded in 1969 by Jerry Sanders, who like Gordon Moore and Robert Noyce, was also at Fairchild semiconductor. Like Intel, they started as a memory chip company, but pivoted to microprocessors in the 1980s. Till the 2000s, they were mostly seen as a laggard to Intel. In fact, the only reason they got Intel's x86 license was that in 1982, IBM forced Intel to declare a second source for x86 compatible chips, and Intel chose AMD. Given this history, September 23 2003 was a key milestone for AMD - on this day, they launched the first 64-bit CPU - the Athlon 64. This processor used AMD's x86-64 ISA - which was an extension to x86 that AMD created. This was one of AMD's biggest architectural wins of that time - as I mentioned before, 64 bit processors meant that physical addresses beyond 4 GB could now be accessed. This was the start of AMD's many architectural wins over Intel from the 2000s till today, which have given them a dominant position in the CPU market.

Apple's unified ecosystem with 64 bit mobile CPUs

It took many years after AMD's Athlon 64 moment for mobile processors to adopt 64-bit. This was primarily because of the low power and area requirements in mobile - the performance boost that 64-bit offered was not as important in mobile. So, in 2013, when Apple announced the iPhone 5s would launch with ARM's 64-bit CPU in the A7 chip, a few eyebrows were raised - especially considering that the RAM was just 1 GB. (none of the phones in 2013 had a RAM of more than 4 GB, so everyone expected 32-bit CPUs to offer the best performance per watt) Looking back, this decision from Apple was actually a masterstroke. Apple introduced 64-bit in the Mac in 2009, and quickly realized that the future of computing is going to be 64-bit. Since Moore's law had done enough by 2013 to enable 64-bit CPUs for mobile (as ARM showed with their CPU core), Apple jumped at the opportunity. By moving both its desktop and mobile platforms to 64-bit, Apple ensured that developers could create more powerful and efficient applications across all its devices. This transition also helped maintain consistency and compatibility within Apple's ecosystem, making it easier for users to switch between devices seamlessly. Over the years, Apple has deprecated 32-bit applications (which slowed down overall performance), and has also moved to custom CPU cores for all their products. This has played a key role in their mobile processor dominating the industry.

In general, bigger CPU's have the potential to be more performant. However, the final result depends on the CPU microarchitecture and assumptions being made - as we saw in mobile CPUs, 64-bit was delayed until it was really needed. So increasing CPU bitness frequently is not always a good idea - in fact, we may never really need 128-bit CPUs for the foreseeable feature. But bitness did play a key role in early processors, and when used smartly, helped companies differentiate their products and gain an advantage.

To compare performance, I think a better metric is to consider the CPU bitness multiplied by the frequency at which the CPU is running - assuming the same ISA, and same target application, this product roughly translates to the number of bits being processed per second - a sign of the performance.

References:

Chip Insights

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